The present invention relates to the fabrication of integrated circuits on semiconductor substrates. More specifically, the present invention relates to a method for fabricating a combination of memory devices and logic devices on the same semiconductor substrate.
As greater and greater numbers of devices and circuits become possible on semiconductor integrated circuits, the desire to integrate more system function onto a single chip grows as well. Logic circuits process, while memory circuits store, information, and the two are used in tandem to add "intelligence" to electronic products. The two functions have been provided on separate chips, adding complexity and cost to the final product. There is an increasing need to join both memory and logic circuits together on the same chip.
With the advent of Large Scale Integration (LSI) many of the integrated circuits formed on semiconductor substrates are comprised of several circuit functions on a single chip. For example, dynamic random access memory (DRAM), nonvolatile memory (NVM), and similar memory devices are composed of an array of memory cells for storing digital information, while the peripheral circuits on these devices are typically composed of logic circuits for addressing the memory cells, with other peripheral circuits functioning as read/write buffers and sense amplifiers.
The field effect transistor (FET) of a semiconductor integrated circuit controls current conduction from a source region to a drain region by application of voltage to a gate conductor. If the gate conductor is insulated from the source-drain conduction channel, the device is called an insulated gate FET. The most common gate structure is that of metal oxide semiconductor (MOSFET).
Dopant atoms are introduced into MOSFETs for specific purposes such as to control threshold voltage, dope gate conductors, or to control substrate currents, with adverse side effects accepted as necessary by-products of dopant atom introduction.
The technology for dynamic random access memory (DRAM) circuits is optimized for density and low cost while the technology for logic circuits is optimized for speed. The requirement for dual work function (i.e., logic and memory) places additional problems of complexity and cost on the fabrication process. Memory circuits achieve density requirements with self-aligned contacts, which are easily implemented in a process having a single type (typically n-type) gate work function. A buried-channel p-type MOSFET is used in DRAM since it allows a single work function gate conductor (n-type) to be employed throughout the technology. This results in cost savings in DRAM, at the expense of an inferior performing p-type MOSFET. P- and n-gate conductor devices are highly desirable for merged logic dram (MLD) products. The fabrication of dual work function n-type and p-type gate conductors comprising CMOS devices necessitates a number of complex photoresist and masking steps which increase cost and decrease yield.
A prior art method for obtaining memory arrays with high density and borderless bitline contacts (borderless to adjacent gate conductor) involves using a gate cap of nitride on top of the polysilicon or composite polysilicon/silicide gate stack conductor. The nitride caps are required in narrow space array memory areas to provide protection against bitline-to-gate conductor shorts. In the prior art method for logic circuits, there is no nitride cap, and each polysilicon gate type may be created by ion implanting from above with the appropriate material. However, use of a nitride cap in the logic circuit preparation would block off the ion implantation and frustrate the necessary doping operation. Problematically, a cap is needed on narrow space array memory gates due to memory device density. There is thus a dual requirement to provide a gate cap on narrow space array gate stacks and to dope each polysilicon gate type.
U.S. Pat. No. 5,668,035 discloses a method for fabricating a dual-gate oxide for memory having embedded logic by forming gate electrodes having thin gate oxide in the logic device areas (peripheral areas) and a thicker gate oxide in the memory cell device areas. The method for dual gate oxide thickness is disclosed as being also applicable to complimentary metal oxide semiconductor (CMOS) circuits where both p-doped and n-doped wells are provided for making p- and n-channel FETs.
U.S. Pat. No. 5,710,073 discloses a method for forming a local interconnect structure using a configuration of spacers and etch barriers (silicon nitride cap layers) to form self-aligned source and drain contacts. The as disclosed process (1) forms isolation caps having anti-reflective properties on the tops of the gate electrodes and on top of first level interconnects; (2) uses highly selective silicon nitride etches for defining the isolation caps; and (3) forms self-aligned first and second level substrate contacts using isolation spacers on the gate electrodes and on the first level insulation layer.
U.S. Pat. No. 5,545,581 discloses a method for forming a plug trench strap by formation of strap holes exposing the electrical elements utilizing an oxide insulation layer, a nitride etch stop, a highly selective oxide nitride etch, and a selective nitride oxide etch.
U.S. Pat. No. 5,492,857 discloses a silicon on sapphire CMOS device for wireless communication.
U.S. Pat. No. 4,350,992 discloses an n-channel MOS or ROM structure. In an array of rows and columns of the cells in accordance with U.S. Pat. No. 4,350,992, the row address lines and gates are polysilicon, and column lines forming output and ground are defined by elongated N+ regions which are partly diffused and partly implanted since the column lines cross beneath the polysilicon row address strips. Each potential MOS transistor in the array is programed to be a logic "1" or "0" by the presence or absence of a moat beneath the gate of a cell.
U.S. Pat. No. 3,899,363 discloses a silicon semiconductor FET utilizing ion implantation to reduce sidewall conduction. The method for reducing the subthreshold sidewall conduction between the source and drain of a FET which is surrounded by recessed oxide comprises the step of doping by ion implantation at least the channel region of said FET at the interface of said channel region with said surrounding recessed oxide to increase the threshold at the edges of said channel region in the vicinity of said recessed oxide.
U.S. Pat. No. 5,304,503 discloses an EPROM (erasable programmable read only memory) cell with a tungsten gate. A process flow is disclosed for fabricating a self-aligned stacked gate EPROM cell that uses a chemical vapor deposition tantalum oxide film to replace conventional oxide-nitride-oxide as a control gate dielectric. The dielectric deposition and cell definition steps of the process flow are performed in a backend module, minimizing high temperature exposure of the tantalum oxide film.
None of the references discussed above describe the formation of dual work function devices without the need for additional masking levels. There thus remains a need for an improved method to provide a memory logic device product having a combination of n-type and p-type gate stack conductors on the same chip including a gate cap which is required for a diffusion conduct which is borderless or self-aligned to the gate conductor. There further remains a need for a method for forming a combination of n-type and p-type gate conductors on the same chip while minimizing the number of photoresist masking operations.